GaAs technology has been in use for many years, but has not achieved commercial viability. A few select applications where performance is the important issue have been addressed. However, widespread acceptance of GaAs technology depends upon price and therefore yield. The yield of GaAs integrated circuits suffers from the small noise margins of presently available GaAs E/D MESFET logic families, as compared to silicon logic families. The small noise margin of presently available GaAs logic families does not allow for enough process variations in the manufacture of GaAs integrated circuits. Drastic yield reductions are especially observed at Large Scale Integration (LSI) levels.
Noise margin of a logic circuit may be defined as the extraneous signal voltage amplitude that can be added algebraically to the noise free worst-case input level before the output voltage deviates from the desired level. Simply put, if a logic gate has too low a noise margin, it will be highly susceptible to unintentional switching by spurious noise signals.
The voltage swing for digital logic circuits (i.e., the swing between the logic "0" voltage and the logic "1" voltage must be large enough to tolerate process variations, temperature effects, and real circuit conditions (such as bus drops, fan in and fan out) and still have sufficient noise margin to tolerate voltage degradations from capacitative coupling, resistive coupling, or radiation.
The simplest GaAs FET logic family that employs both depletion and enhancement mode MESFETs is Direct Coupled FET Logic (DCFL). A DCFL inverter may be implemented using an enhancement mode (i.e., normally off) GaAs MESFET whose source terminal is connected to ground and whose gate terminal receives the input signal. This FET serves as the driver for the inverter. A load is connected between a voltage source V.sub.DD and the drain terminal of the driver MESFET. The signal output of the inverter is taken at the drain terminal of the driver MESFET. A depletion mode (i.e., normally on) MESFET is used as an active non-linear load element. The drain of the load FET is connected to the voltage source V.sub.DD and the source of the load FET is connected to the drain of the driver FET. The gate of the load FET is tied to its source. Typically, V.sub.DD is about 1 Volt for DCFL.
In the inverter described above, when the voltage on the gate of the driver FET is low (i.e., logic "0") the driver FET is not conducting and its drain (i.e, the output terminal) is "pulled up" to the high voltage value by the load. When the voltage on the gate of the driver FET is high (i.e, logic "1") the driver is conducting and its drain terminal is "pulled down" to the low voltage value.
Circuits other than an inverter may be realized in DCFL. For example, a two input NOR gate is obtained by connecting a second enhancement-mode driver FET in parallel with the first driver FET. In this case, if the gate of either or both driver FETS is high, the output is low. If the gates of both driver FETs are low, tee output is high. Similarly, a two input NAND gate may be formed by connecting a second driver FET in series with the first driver FET.
For the DCFL logic family, the logic "0" voltage value is about 0.2 Volts. However the logic "1" voltage value is only about 0.7 volts. Thus, the voltage swing between the logic "0" and logic "1" voltage values is only about 50% of the supply voltage V.sub.DD, which, as indicated above, has a value of about 1 volts. The limit on the logic "high" voltage value occurs because of the Schottky barrier diode between the gate and source terminals of the enhancement mode driver MESFET of the DCFL gate. When this intrinsic diode is forward biased its voltage drop is 0.7 volts.
The biggest drawback of DCFL is in its low noise margin. The threshold voltage for switching a typical GaAs enhancement mode MESFET is about 200 millivolts. Similarly, the threshold voltage for switching a DCFL gate is about 400 millivolts depending on the relative dimensions of the enhancement and depletion mode driver and load MESFETs. This gives DCFL a nominal noise margin which is insufficient to overcome process variations, temperatures effects, real circuit conditions (such as bus drops, fan in and fan out) and voltage degradations resulting from capacitative coupling, resistive coupling or radiation.
A number of modifications have been proposed to overcome the low noise margin of the DCFL logic family. In one such logic family, known as Enhancement/Depletion Buffered FET Logic (E/D BFL), the threshold for switching the basic DCFL inverter is increased by placing a Schottky barrier diode in series between the enhancement mode driver FET source terminal and ground, thereby increasing the effective switching threshold voltage by the voltage drop of the added diode. However, this diode merely serves to level shift the high and low voltage levels. The high (i.e., logic "1") voltage level is about 1.4 volts or twice the voltage drop of a Schottky barrier diode and the low (i.e., logic "0") voltage level is about 0.7 volts or equal to the voltage drop of one Schottky barrier diode. For this reason a source follower stage is used as an output stage for the E/D BFL gate. E/D BFL provides a noise margin slightly better than DCFL.
Illustratively, the source follower stage comprises an enhancement mode MESFET whose gate terminal is connected to the output of the inverter stage, whose drain terminal is connected to a voltage supply, and whose source terminal is connected to a load. The source of the enhancement mode FET forms the output of the source follower stage. Illustratively, the load may be a depletion mode MESFET whose source is tied to its gate. The drain of the depletion load MESFET is connected to the source of the enhancement mode MESFET and the source of the depletion mode load MESFET is connected to ground.
In an alternative prior art family of logic known as Low Pinch-Off FET LOGIC (LPFL), instead of modifying the basic DCFL inverter by connecting a Schottky barrier diode between the source terminal of the driver FET and ground, an improved noise margin may be achieved by placing a diode in the source follower stage so that its anode is connected to the source of the enhancement mode FET and its cathode is connected to the drain of the depletion mode load FET. The output is taken at the cathode of the diode.
However, the foregoing logic families suffer from a number of substantial shortcomings. First, DCFL, E/D BFL and LPFL all have output voltage swings equal to about 60% or less of the supply voltage V.sub.DD. Furthermore, the E/D BFL and LPFL logic families utilize a source follower in the output stage which constantly draws DC power even when not required to charge interconnect capacitances. Lastly, for DCFL, large input FETS must be used which add extra input capacitance and can make the circuit area larger than other prior art circuits such as the two stage circuits of the E/D BFL and LPFL families even though DCFL has fewer components.
Accordingly, it is an object of the present invention to provide a new family of GaAs logic which overcomes the foregoing shortcomings and which provides fast switching speed and lower power dissipation. More particularly, it is an object of the present invention to provide a high performance logic family which may be implemented using enhancement and depletion mode GaAs MESFETs, which logic family achieves a large noise margin without the penalties of high power dissipation or long switching delays.